ISA215-HYD module reverse engineering => involved in p1a15-error-condenser-charge-timeout

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Sorry for poor image, this is a screenshot of a picture, haven't found this notebook yet. My note indicates that all the control lines were tied together from the 7.5V bias of the divider. Why could this not be done?

Screenshot 2024-03-30 at 3.06.02 PM.png
The Control pins of the 4066 are always active, held high by a voltage divider described in a post #19.
? Surely not all of them. It looks to me that only 2 inputs are so held.

But keeping a control pin high (active) turns that element into a resistor. That seems pointless to me, unless it's to match with temperature change the resistance of the other elements when they are switched on.

Am I missing something?
Looked at the board again.

There was a marking on the diode but couldn't make it out clearly; sometimes i thought it read "5.5" but then i blink and its something else. i could put a voltage across it and measure the zener drop if necessary.

All the control line pins measured direct continuity to the output of the voltage divider as previously described.

But the "15V" supply for the divider is tied to the TL494 pin 11, collector for PWM switching Q2 circuit, which is tied to pin 3 on the primary of "T24:" Mod transformer. The center tap pin 4 is tied to the 15V supply, and pin 5 tied to the TL494, pin8, the collector of PWM Q1.

So the 4066 control pins are being pulsed in synch with the PWM. The switches would pass the signal thru only when it was valid.
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I think I know.
TL494 runs as a free PWM generator , open loop . But the duty cycle must be nevetheless fixed. So the input pin feedback must be set to a precise voltage.
This voltage is compared to the oscillator ramp ( have a look to functionnal block diagram).
It is the purpose of this voltage divider.

It is normal to find a 4066 control pins tight together _statically_ because they are connected through transformer (have a look on my schematics). Dynamically it is not the case (hopefully)

bellow my last proposal. resistor divider and logical inverter added


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oscillator ramp is between 0V to 3V, so voltage divider output, when board is 15V powered, should be somewhere around 1.5V if 50% DC is required

best regards
I'm very interested about those resistances value : two solutions
1/power the board with a known voltage and measure resistor divider voltage or
2/desolder one of them to measure each one.

who can do that?
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i measured 15k each this morning for the voltage divider resistors.

This is a different board than was used for the measurements of post #19 (notes from Justin's troubleshooting).

i could find no connection for pin 3 of the TL494 to anything on the board.
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mmm , yes... and if you power the board with 12V what is the voltage on that pin?
pin 3 is the comparator input for PWM, as the internal current generator drawn 700µA I cannot imagine the voltage to be stuck to zero.
unless one error amp pushs the pin3 to the max PWM value
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okay... so by reading the DS, duty cycle is pushed to the max when pin 3 is down to zero.. right.
And deadtime input , with the RC circuitry is a kind of soft start as well. good.
You will consider me as a psycho!
I realize that circuitery could be exactly as our friend Kiev sketch it...
the point is ... the control line of ALL the CMOS are connected together.. it is indeed visible on picture.
... so they are ALL switched together also..
but not all the time.
I think that this creazy designers add the resistor at the power input intionnally to create a little drop in the power line when TL494 conduct (and draw current)
that's why the resistor devider is exactly at the middle of Vcc, it is the balance point ! when Vcc drop a little all switches are open ... it is like a sample and hold...
oh my godness!

could I have the input resistance value?
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i powered up the hybrid board with 15VDC and made some scope traces and probed voltages.

With 2.036V applied to pin 1 the Input (VH) terminal, i measured 2.059V at the pin 3 Output terminal. As expected from a Unity gain isolation amplifier, and within about 1% this is good to know.

The voltage divider is not connected to the supply, but is on the Q2 side of the Center-tap Primary Winding. The Center tap is connected to the supply and there is about 8 Ohms to each side. There is about 27V pk-pk at the Primary, and the voltage divider output is 13.6V switching at 54kHz.
Voltage Divider Output to TL494 .jpg

The Q1pink Q2 green pair are switching the Primary at about 54kHz,
Q1 pink Q2 grn.jpg

The voltage at pin 3 of the TL494 was about 60mV
Pin3 of Output 4066.jpg

Here are the demod transformer secondary outputs to the 4066 with 2V on the Input. This feeds into the A-B pair that is on the Hi Side (the Output).

Demod Sec to top 4066 A&B with 2V at VH.jpg

And the C-D pair feed that makes the Lo Side (ground). The scope reference has been adjusted in order to view the entire signal pulse (ringing and float when the switch is in off state).
Demod Secondary feeds top 4066 C&D Lo Side.jpg

The resistors on the input to the op amp are 100k on the inverting and feedback, and 50k on the non-inverting.

Which resistors are you asking for? i'm not understanding your request.
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excellent ! I think we are close to the goal :
my proposal for the schematic with your last update bellow
it is quite normal to have the R divider to feed 4066 with transformerr signal.
because of the topology , max voltage seen on the transformer rise up to 2xVcc, here about 30V (transformer effect) , so it is necessary to scale it down by a 2 factor.
all the output 4066 switch perform a sample and hold. ... simply
I also did a small simulation.... it seems OK


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The low voltage supplies created from the secondary of the oscillator measured +7.38 and -7.51 at the vias near the rectifier diode. This reflects from the peak voltage of the flats out of the secondary (+8 and -8.4)
8v4 on negative side.jpg
Here are a couple of scope traces on the Output before and after the Low Pass Filter with the same 2.036V on the Input. Shows good agreement with the voltmeter measurement of 2.059 on Output. The ripple frequency before the LPF was at about 53.3 kHz.

Pre LPF with 2V Input.png

Output with 2V Input.png
Those values are probably what they used, my values were from measurement with tweezers.

testing kicad drawing (jpeg image)
hybrid schema wip.png
[too small i can't see or read the jpeg version]

trying a pdf [works better for viewing to me]
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