as I told before.... stifness is largely hampered by pcb milling (creepage purpose) , pin holding only at each end of the board and heavy component in the middle.
I really don't know what was in designer's head .
adding a resistor into a power line is a newbee fault, logical circuit really don't like that.
moreover if it is for filtering purpose, the guy added a cap in // so he also jeopardise the "filter behaviour", it is ridiculous.
okay, here find my sch in pdf print shape.
added value (they are crazy to add such a R inline with the power!), also renumbered all topos
you can zoom in as far as you want :)
excellent ! I think we are close to the goal :
my proposal for the schematic with your last update bellow
it is quite normal to have the R divider to feed 4066 with transformerr signal.
because of the topology , max voltage seen on the transformer rise up to 2xVcc, here about 30V (transformer...
You will consider me as a psycho!
I realize that circuitery could be exactly as our friend Kiev sketch it...
the point is ... the control line of ALL the CMOS are connected together.. it is indeed visible on picture.
... so they are ALL switched together also..
but not all the time.
I think that...
okay... so by reading the DS, duty cycle is pushed to the max when pin 3 is down to zero.. right.
And deadtime input , with the RC circuitry is a kind of soft start as well. good.
mmm , yes... and if you power the board with 12V what is the voltage on that pin?
pin 3 is the comparator input for PWM, as the internal current generator drawn 700µA I cannot imagine the voltage to be stuck to zero.
unless one error amp pushs the pin3 to the max PWM value
I'm very interested about those resistances value : two solutions
1/power the board with a known voltage and measure resistor divider voltage or
2/desolder one of them to measure each one.
who can do that?
oscillator ramp is between 0V to 3V, so voltage divider output, when board is 15V powered, should be somewhere around 1.5V if 50% DC is required
best regards